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Author Teubner, Jens.
Title Data processing on FPGAs [electronic resource] / Jens Teubner, Louis Woods.
Publication Info. San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, c2013.
Location Call No. Status Notes
 Libraries Electronic Books  ELECTRONIC BOOKS-DDA    AVAIL. ONLINE
Description 1 online resource.
Series Synthesis digital library of engineering and computer science.
Synthesis lectures on data management ; # 35. 2153-5426
Note Part of: Synthesis digital library of engineering and computer science.
Title from PDF t.p. (viewed on July 18, 2013).
Series from website.
Bibliography Includes bibliographical references (p. 95-100) and index.
Contents 1. Introduction -- 1.1 Moore's law and transistor-speed scaling -- 1.2 Memory wall and Von Neumann bottleneck -- 1.3 Power wall -- 1.4 Multicore CPUs and GPUs -- 1.5 Specialized hardware -- 1.6 Field-programmable gate arrays (FPGAs) -- 1.7 FPGAs for data processing -- 1.7.1 Stream processing -- 1.7.2 Big data -- 1.7.3 Cloud computing -- 1.7.4 Security --
2. A primer in hardware design -- 2.1 Basic hardware components -- 2.1.1 Combinational logic -- 2.1.2 Sequential logic -- 2.1.3 Asynchronous sequential logic -- 2.1.4 Synchronous sequential logic -- 2.2 Hardware programming -- 2.2.1 Hardware description languages (HDLs) -- 2.3 Circuit generation -- 2.3.1 Logical design flow (Synthesis) -- 2.3.2 Physical design flow --
3. FPGAs -- 3.1 A brief history of FPGAs -- 3.2 Look-up tables, the key to re-programmability -- 3.2.1 LUT representation of a Boolean function -- 3.2.2 Internal architecture of an LUT -- 3.2.3 LUT (Re)programming -- 3.2.4 Alternative usage of LUTs -- 3.3 FPGA architecture -- 3.3.1 Elementary logic units (Slices/ALMs) -- 3.4 Routing architecture -- 3.4.1 Logic islands -- 3.4.2 Interconnect -- 3.5 High-speed I/O -- 3.6 Auxiliary on-chip components -- 3.6.1 Block RAM (BRAM) -- 3.6.2 Digital signal processing (DSP) units -- 3.6.3 Soft and hard IP-cores -- 3.7 FPGA programming -- 3.7.1 FPGA design flow -- 3.7.2 Dynamic partial reconfiguration -- 3.8 Advanced technology and future trends -- 3.8.1 Die stacking -- 3.8.2 Heterogeneous die-stacked FPGAs -- 3.8.3 Time-multiplexed FPGAs -- 3.8.4 High-level synthesis --
4. FPGA programming models -- 4.1 Re-build, parameterize, or program the hardware accelerator? -- 4.1.1 Re-building circuits at runtime -- 4.1.2 Parameterized circuits -- 4.1.3 Instruction set processors on top of FPGAs -- 4.2 From algorithm to circuit -- 4.2.1 Expression [to] circuit -- 4.2.2 Circuit generation -- 4.2.3 High-level synthesis -- 4.3 Data-parallel approaches -- 4.3.1 Data parallelism -- 4.4 Pipeline-parallel approaches -- 4.4.1 Pipeline parallelism in hardware -- 4.4.2 Pipelining in FPGAs -- 4.4.3 Designing for pipeline parallelism -- 4.4.4 Turning a circuit into a pipeline-parallel circuit -- 4.5 Related concepts --
5. Data stream processing -- 5.1 Regular expression matching -- 5.1.1 Finite-state automata for pattern matching -- 5.1.2 Implementing finite-state automata in hardware -- 5.1.3 Optimized circuit construction -- 5.1.4 Network intrusion detection -- 5.2 Complex event processing -- 5.2.1 Stream partitioning -- 5.2.2 Hardware partitioner -- 5.2.3 Best-effort allocation -- 5.2.4 Line-rate performance -- 5.3 Filtering in the data path -- 5.3.1 Data path architecture in the real world -- 5.4 Data stream processing -- 5.4.1 Compositional query compilation -- 5.4.2 Getting data in and out -- 5.5 Dynamic query workloads -- 5.5.1 Fast workload changes through partial modules -- 5.6 Bibliographic notes --
6. Accelerated DB operators -- 6.1 Sort operator -- 6.1.1 Sorting networks -- 6.1.2 BRAM-based FIFO merge sorter -- 6.1.3 External sorting with a tree merge sorter -- 6.1.4 Sorting with partial reconfiguration -- 6.2 Skyline operator -- 6.2.1 Standard block nested loops (BNL) algorithm -- 6.2.2 Parallel BNL with FPGAs -- 6.2.3 Performance characteristics --
7. Secure data processing -- 7.1 FPGAs versus CPUs -- 7.1.1 Von Neumann architecture -- 7.1.2 Trusted platform module (TPM) -- 7.2 FPGAs versus ASICs -- 7.3 Security properties of FPGAs -- 7.3.1 Bitstream encryption -- 7.3.2 Bitstream authentication -- 7.3.3 Further security mechanisms -- 7.4 FPGA as trusted hardware -- 7.4.1 Fully homomorphic encryption with FPGAs -- 7.4.2 Hybrid data processing -- 7.4.3 Trusted hardware implementation --
8. Conclusions -- A. Commercial FPGA cards -- A1. NetFPGA -- A2. Solarflare's applicationOnload engine -- A3.Fusion I/O's ioDrive -- Bibliography -- Authors' biographies -- Index.
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Reproduction Electronic reproduction. Perth, W.A. Available via World Wide Web.
Subject Field programmable gate arrays.
FPGA
modern hardware
database
data processing
stream processing
parallel algorithms
pipeline parallelism
programming models
Added Author Woods, Louis.
Ebooks Corporation
Related To Print version: 9781627050609
ISBN 9781627050616 (electronic bk.)
1627050612 (electronic bk.)
9781627050609 (pbk.)
Standard No. 10.2200/S00514ED1V01Y201306DTM035 doi
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