| Description |
1 online resource. |
|
text txt rdacontent |
|
computer c rdamedia |
|
online resource cr rdacarrier |
| Series |
Synthesis lectures in computer architecture ; #20. 1935-3235
|
| Bibliography |
Includes bibliographical references (pages 71-81). |
| Reproduction |
Electronic reproduction. Perth, W.A. Available via World Wide Web. |
| Note |
Online resource; title from PDF title page (Morgan & Claypool, viewed Nov. 27, 2012). |
| Contents |
1. GPU design, programming, and trends -- 1.1 A brief history of GPU -- 1.2 A brief overview of a GPU system -- 1.2.1 An overview of GPU architecture -- 1.3 A GPGPU programming model: CUDA -- 1.3.1 Kernels -- 1.3.2 Thread hierarchy in CUDA -- 1.3.3 Memory hierarchy -- 1.3.4 SIMT execution -- 1.3.5 CUDA language extensions -- 1.3.6 Vector addition example -- 1.3.7 PTX -- 1.3.8 Consistency model and special memory operations -- 1.3.9 IEEE floating-point support -- 1.3.10 Execution model of OpenCL -- 1.4 GPU architecture -- 1.4.1 GPU pipeline -- 1.4.2 Handling branch instructions -- 1.4.3 GPU memory systems -- 1.5 Other GPU architectures -- 1.5.1 The Fermi architecture -- 1.5.2 The AMD architecture -- 1.5.3 Many integrated core architecture -- 1.5.4 Combining CPUs and GPUs on the same die. |
| Subject |
Graphics processing units.
|
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Parallel processing (Electronic computers)
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GPGPU |
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performance analysis |
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performance modeling |
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CUDA |
| Added Author |
Kim, Hyesoon, 1974-
|
|
Ebooks Corporation
|
| Related To |
Print version: Performance analysis and tuning for general purpose graphics processing units (GPGPU). [San Rafael, Calif.] : Morgan & Claypool, ©2012 9781608459544 |
| ISBN |
9781608459551 (electronic bk.) |
|
1608459551 (electronic bk.) |
|
9781608459544 (paperback) |
| UPC # |
10.2200/S00451ED1V01Y201209CAC020 doi |
| OCLC # |
EBC1092425 |
|
